The present invention relates to a semiconductor device having nonvolatile memory cells of multi-storage forms, wherein a structure called “a so-called MNOS (Metal Nitride Oxide Semiconductor)” or “MONOS (Metal Oxide Nitride Oxide Semiconductor)” is configured as a base, and electrons are trapped in nitride near the interface between nitride and oxide at physically different positions, thereby making it possible to perform the storage of multi-valued information, an IC card using the semiconductor device, and a method for manufacturing such a semiconductor device. The present invention also relates to, for example, a technology effective for application to a microcomputer for an IC card provided with a nonvolatile memory of a multi-storage form on an on-chip basis.
A nonvolatile memory cell having a MONOS structure has been described in U.S. Pat. No. 5,768,192. According to this, as illustrated in FIGS. 45(A) and 45(B), a gate oxide film 1 and a gate nitride film 2 are laminated on a semiconductor region, and a memory gate electrode 3, which constitutes a word line, is provided thereon. Further, signal electrodes 4 and 5 either of which serves as a source or drain electrode, are formed in the semiconductor region placed under the memory gate electrode. The present nonvolatile memory cell is capable of trapping electrons in the gate nitride film 2 near the interface with the gate oxide film 1 at physically different positions, thereby performing the storage of multi-valued information. The injection of electrons in nitride is carried out according to channel hot electron injection. When one attempts to inject hot electrons into the right end of the gate nitride 2 as shown in FIG. 45(A), the left signal electrode 5 is used as a source (source (W)), and the right signal electrode 4 is used as a drain (drain (W)). Further, a drain current is caused to flow so that the direction indicated by arrow W takes the direction of motion of electrons. Thus, the electrons in a channel are accelerated under a high electric field near the drain and thereby brought into hot electrons, followed by injection into the drain end of the gate nitride film 2. When it is desired to inject hot electrons into the left end of the gate nitride film 2 as shown in FIG. 45(B), the right signal electrode 4 is used as a source (source (W)) and the left signal electrode 5 is used as a drain (drain (W)), and electrons are moved in the direction indicated by arrow W.
When information stored at the right end of the gate nitride film 2 is read as shown in FIG. 45(A), the right signal electrode 4 is used as a source (source (R)) and the left signal electrode 5 is used as a drain (drain (R)), and the memory gate electrode 3 may be set to a select level. Since a depletion layer of a MOS transistor expands into the drain side, the switch state of the memory cell greatly depends on the state of a threshold voltage on the source side. Thus, when information stored at the left end of the gate nitride film 2 is read as shown in FIG. 45(B), the left signal nitride 5 and the right signal electrode 4 are respectively used as a source (source (R)) and a drain (drain (R)) so that the sources and drains are set contrary to FIG. 45(A), and the memory gate electrode 3 may be set to a select level. If an erase state in which the threshold voltage is lower than the gate select level, is taken, then electrons flow in the direction indicated by arrow R.
A plan view of one memory cell is illustrated in FIG. 45(C). F means a minimum processed size. FIG. 46(A) illustrates voltage-applied states necessary for an erase (e.g., electron discharge) operation based on word-line units, FIG. 46(B) illustrates voltage-applied states necessary for an erase operation based on a memory array batch, FIG. 46(C) illustrates voltage-applied states necessary for writing (e.g., injection of electrons), and FIG. 46(D) illustrates voltage-applied states necessary for reading, respectively. In FIGS. 46(A) through 46(D), portions indicated by elliptical circles affixed to the memory cells respectively means regions intended for writing, erasing and reading.